1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular, including a redundant memory cell substitution circuit which selects a redundant memory cell instead of a defective memory cell. This is a counterpart of and claims priority to Japanese Patent Application No. 2003-209149 filed on Aug. 27, 2003, which is herein incorporated by reference.
2. Description of the Related Art
In the related art, a semiconductor memory device has a memory cell array consisting of a plurality of the memory cell blocks arranged in matrix. Each of the memory cell blocks includes a plurality of memory cells arranged in matrix. A redundant memory cell array consisting of a plurality of redundant memory cells is disposed in each of the memory cell blocks. The redundant memory cell is used instead of a defective memory cell. The redundant memory cell array has an array in a row direction and an array in a column direction, and the redundant memory cell is selected instead of the defective memory cell in each of the row and column directions. It is necessary to use a redundant memory cell substitution circuit that comprises a fuse block and an address matching detector. The fuse block has information with respect to an address of the defective memory cell for which the redundant memory cell is substituted. The address matching detector checks whether an external address signal input in the semiconductor memory device corresponds to the address of the defective memory cell or not, in order to select the redundant memory cell instead of the defective memory cell. However, recently, the semiconductor integrated circuit is made finer, and on the other hand, the number of the redundant memory cell array is increasing in the semiconductor memory device for the purpose of improving the process yield of the semiconductor memory device. Therefore, the proportion of the redundant memory cell substitution circuit to the memory cell array in the area of the semiconductor integrated circuit is increasing, and there is room for improvement of the miniaturization in the semiconductor device. To decrease the above-mentioned proportion of the redundant memory cell substitution circuit, the invention of the semiconductor memory device has been proposed as described in Documents 1 (Japanese Patent Publication Laid-Open No. Hei 14(2002)-015593) and Document 2 (Japanese Patent Publication Laid-Open No. Hei 07(1995)-211779).
In the semiconductor memory device as described in the Document 1 (in particular, Pages 8–9 and FIG. 3), one fuse block is formed so as to access to a redundant memory cell instead of a defective memory cell in either the row direction or the column direction. As the result, the amount of fuses can be decreased, and the area covered with the fuses can be decreased.
In the semiconductor memory device as described in the Document 2 (in particular, Pages 4–6 and FIGS. 1 and 2), the leakage current is prevented by P-type wells which is made smaller in the surface of the N-type well formed in the forming step of the P-type MOS (Metal Oxide Semiconductor) transistor. That is, the intervals between a plurality of the arranged fuses is decreased by forming the smaller P-type wells which can prevent the leakage current with every fuse. Therefore, the area in which the fuses are disposed can be decreased.
However, in the above-mentioned semiconductor memory device as described in Document 1, though the fuse block can be used to have access to the redundant memory cell instead of the defective memory cell in both the row direction and the column direction, the address matching detectors are needed as much as the number of the fuse blocks. That is, in the device in the Document 1, it is necessary that the area of the redundant memory cell substitution circuit is further decreased. Also, in the above-mentioned semiconductor memory device as described in the Document 2, though the area in which the fuses are disposed is decreased by decrease the intervals between a plurality of the arranged fuses, it is not disclosed that the area of the address matching detectors is decreased. Therefore, it is necessary that the area of the redundant memory cell substitution circuit is further decreased in the device in the Document 2, too.